This invention pertains to a fully 2's complement floating-point multiply accumulate (FMAC) unit, and more particularly to a 2's complement FMAC producing an unrounded, inverted 2's complement result which is associated with a single INC bit (increment bit). A 2's complement FMAC has significant advantages over conventional signed magnitude FMAC's in that hardware components, including an entire adder, may be eliminated. Eliminating hardware not only reduces the costs to manufacture an FMAC, but also frees up space on the surface of an integrated circuit (IC). Those versed in the art appreciate the fact that use of surface area of an IC carries a premium, especially in the case of a VLSI (very large scale integrated) circuit such as a microprocessor.
In the design of microprocessor architecture, three very important considerations are speed, accuracy and cost. While it is desirable to design a microprocessor (CPU) which performs multiplication, addition and other operations with superior accuracy and at a very high rate of speed, it is also desirable to design a CPU which can be cost effectively manufactured.
Speed and accuracy have been greatly increased in recent years by fusing multiply and add operations into the accumulate operation (A*B)+C. If it is desired to merely add or multiply two numbers, the operation A*B can be performed by setting C=0, and the operation A+C can be performed by setting B=1. The component of a CPU which performs the (A*B)+C operation is commonly referred to as an FMAC (floating-point multiply accumulate unit) or MAF/FPU (multiply-add-fused floating-point unit). A conventional MAF/FPU design is disclosed by R. K. Montoye, E. Hokenek, and S. L. Runyon in "Design of the IBM RISC System/6000 Floating-Point Execution Unit," IBM J. Res. Develop. 34, 61-62 (January 1990).
The inputs to an FMAC are the operands A (multiplicand), B (multiplier) and C (addend), where A, B and C are floating-point numbers (floating-point numbers are numbers expressed in scientific notation). IEEE has issued the accepted standards for representing floating-point numbers. ANSI/IEEE Standard for Binary Floating-Point Arithmetic, STD 754-1985, IEEE, New York, Aug. 12, 1985. The convention given for representing single(32-bit) and double-precision (64-bit) floating-point numbers in binary form is S,E,M!, where S is a single bit determining the sign of a number, E is an exponent, and M is a mantissa or fraction (stripped of its leading 1). Thus, the form of an IEEE floating-point number is (-1).sup.s !*2.sup.(E+Bias) !*(1.M). In a single precision system, E is represented by eight bits, and M is represented by twenty-three bits (the twenty-three bit mantissa becomes a twenty-four bit mantissa when the floating-point number is input into an FMAC--operations performed internal to the FMAC require that a mantissa's implied leading 1 be present). In a double precision system, E is represented by eleven bits, and M is represented by fifty-two bits (fifty-three bits while the number is internal to the FMAC). The exponent Bias is 127 (single precision) or 1023 (double precision).
A multiplication of A and B requires multiplication of their mantissas, and addition of their exponents. If the mantissa of A (internal to the FMAC) comprises m-bits and the mantissa of B comprises n-bits, multiplication of their mantissas requires adding A to itself n-times, each time shifting the m-bits of A to the left by one bit. The result of the multiplication is an "m+n+1"-bit mantissa. The addition of (A*B) and C requires alignment of their mantissas through a comparison of the magnitude of their exponents, followed by addition of their mantissas. Using a leading bit anticipator and/or truncation, the accumulate output of an FMAC will be an "m-1"-bit mantissa (the leading 1 is once again stripped), an exponent, and a sign bit (in the form S,E,M). Bits truncated from, or otherwise shifted out of, the "m-1"-bit mantissa output may be used in rounding calculations.
IEEE outlines four rounding modes which a microprocessor, and more specifically an FMAC, must be capable of implementing. The modes are: 1) Round to Positive Infinity (+INF), 2) Round to Negative Infinity (-INF), 3) Round to Zero (ZERO), and 4) Round to Near (NEAR). Definitions and additional details concerning these rounding modes are found in IEEE Standard 754-1985, supra.
Operations such as addition are much simpler when numbers are represented in 2's complement form (i.e., positive numbers remain in signed magnitude form while negative numbers are inverted and then incremented by one). For instance, an add of two signed magnitude numbers requires a combination of two carry propagate adders followed by an end-around carry MUX (multiplexer). An add of two numbers in 2's complement form merely requires a single 2's complement adder. Adders are costly to implement, and detract from an FMAC's speed due to their extensive routing requirements. However, 2's complement notation has yet to be adopted within conventional FMACs. The failure to adopt 2's complement notation is believed to be due to 1) performance delays in converting to and from 2's complement notation, and 2) routing penalties in making an early unrounded FMAC result available as an FMAC operand (i.e., passing two INC bits--one for rounding purposes, and one for the purpose of converting negative numbers back into signed magnitude form).
It is therefore a primary object of this invention to provide a fully 2's complement FMAC.
It is a further object of this invention to provide a 2's complement FMAC in which an entire adder may be eliminated.
It is also an object of this invention to provide a 2's complement FMAC in which an unrounded result associated with a single INC bit may be passed back into the top of an FMAC.
It is yet another object of this invention to provide a 2's complement FMAC in which conversion to and from 2's complement notation may be performed in parallel with, or as a part of, other required operations, such that conversion does not add additional delay to the critical path of the FMAC.
It is also an object of this invention to provide a 2's complement FMAC which results in significant cost savings through the reduction in IC surface area required to implement the FMAC.